SK Hynix`s 96-layer 512gigabit 4D NAND. [Photo provided by SK Hynix]
South Korea’s SK Hynix Sunday, out to reinforce its flash capabilities, has raised the bar in the NAND storage by packaging all the possible next-generation technologies into its new output in four-dimensional, 96-stack, 512-gigabit speed, and TLC (triple level cell) formula, plus the Peri Under Cell (PUC) technology to upgrade the Charge Trap Flash (CTF) structure common for 3D NAND.
CTF is a technology that dramatically enhances performance and productivity by minimizing interference between cells, which was introduced to overcome the drawback of floating gates in the 2D planar NAND flash memory chips. Peri Under Cell is a technology for placing the peripheral circuit that controls the cells at the bottom of data storage cells. Most chipmakers adopt CTF for their 3D NAND flash chips, but the world’s second-largest memory chipmaker is the first in the world to have applied PUC to CTF, from which the name was given to the new chip.
The chip size of the 4D NAND flash is reduced by more than 30 percent from a 72-layer 3D NAND flash, but it provides 30 percent higher write and 25 percent higher read performance. The new 4D chip can replace two 256 gigabit 3D NAND completely, cutting production costs, according to the company.
SK Hynix will release 1 terabit-capacity solid state drive (SSD) equipped with the new 4D NAND flash chip for consumers within the end of this year. The company also plans to switch 72-layer SSD products to 96-layer SSD devices next year with certification from large clients such as HP and MS.
On Monday, shares of SK Hynix closed 2.89 percent lower at 70,500 won ($62.72) in Seoul trading.
By Chun Kyung-woon and Minu Kim
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